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In step 17, a scalar multiplication of result in 31, by the binary representation of the sign polarity, obtained from step 4 and stored in register 5, is performed with the final floating point representation of the ASCII string real number placed in 32. It shows steps and registers involved in a branchless, constant time execution of an ASCII real number to floating point binary decimal conversion within the vector processor. In step 11, the resulting numbers, 19, 20, and 22 are converted to a floating point number by placing a decimal point, followed by a zero, to the right of the last number of each. While the embodiment of FIG. ASCII string real number of any byte size equal to or less than the byte size of the registers provided for by a vector processing architecture, said real number comprising a sign byte, an integer part, a fractional part, a decimal point separating the integer part from the fractional part, and a string terminator, to a binary floating point real number representation of the ASCII string real number on a vector processor having the vector processing architecture, said binary floating point real number representation of the ASCII string real number comprising a positive or negative binary vector value, corresponding to a positive or negative sign byte, respectively of the ASCII string real number and having a magnitude with an integer portion and a fractional portion with a decimal point separating the integer portion from the fractional portion, said method comprising, implementation of code comprising a fixed sequence of a constant number of instructions to execute one or more steps of the conversion, said conversion further comprising, detection of the sign byte, assigning a plus or minus 1 value, dependent on the sign being positive or negative respectively, storing this value in a register of the vector processor, and removing the sign byte from the ASCII string real number; detection of the string terminator, aligning the string to an edge of a vector processor register having byte width equal to or greater than the number of characters in the ASCII string real number and, if the register has a greater byte width than the number of characters in the ASCII string real number, masking all unused characters in from the opposite edge to the aligned edge with zeros resulting in one or more leading or trailing zeros; detecting and storing in a register of the vector processor the decimal point position that separates the integer part of the ASCII string real number from the fractional part of the ASCII string real number and removal of the decimal point from the ASCII string real number; parallel conversion of all one or more characters of the unsigned string, with no decimal point, into corresponding binary coded decimal bytes to form a binary real number having one or more bytes, wherein the number of the one or more bytes corresponds to the number of characters of the unsigned string with no decimal point; parallel multiplication of each of the binary coded decimal values with a power of ten corresponding to the placement of each of the binary coded decimal values inside the binary real number to obtain individual binary results; aggregation of the individual binary results of the parallel multiplication into a first intermediate binary result; multiplication of the first intermediate binary result with a floating point power of ten corresponding to a placement of the decimal point to obtain a second intermediate binary result; and multiplication of the second intermediate binary result with the binary value assigned to the sign to get a final signed floating point binary result. Because numbers, when expressed in ASCII format, can assume arbitrary length, the traditional algorithms solve the problem in a time directly proportional to the length of the string representing the number, and the generated code contains several branches, which can cause severe latency penalties on several modern processing architectures. To achieve this further objective of providing a vector processor capable of performing the conversion with a single instruction, the inherent single instruction multiple data instruction, SIMD, capability of the vector processor is used in combination with code designed with the SIMD function in the design of the vector processor.

Then, each of the decimal components of the real number is multiplied by a power of ten, starting with ten to the zero power, or one, for the least significant digit, ten to the first power, or ten, for the digit to the left of the least significant digit, if applicable, ten to the second power, or one hundred, for the digit to the left of the previous digit, if applicable, etc. The advantage is a substantially higher predictability of the execution time, and higher overall performance on modem vector processors which poorly tolerate intense program flow control. In step 16, a scalar multiplication of the result in 28, from step 14, by the floating point number in 30 is performed and the result placed in 31. This is repeated for as many digits comprising the real number, up to and including the most significant digit. In step 7, binary decimal forty eight is subtracted from each character of the word in the register of step 6 to perform the ASCII to binary decimal conversion of each digit of the real number. Thus the number in the example is comprised of a minus sign, an integer, 234567890, comprising nine digits, a fractional part, 12, consisting of two digits, and a decimal point between the integer and the fractional part. In step 14, a scalar addition is performed on the results in 26 and 27 with the result placed in 28. Each of these products is then accumulated and the sign added, resulting in a binary decimal converted number.

In step 13, a horizontal vector addition is performed on the two adjacent half words in 25 and the two adjacent half words in 24 with the results placed in 26 and 27 respectively. ASCII to Floating point binary decimal real number conversion in a vector processor. ASCII string, within a given range of sizes provided for by the vector processor architecture. In step 1, the first of a fixed number of sequential instructions is executed for the ASCII to floating point binary decimal conversion and the ASCII number is fetched from memory. The real number is detected as being between the sign bit and the string terminator. This is called normalization. ASCII string, still giving a constant, albeit longer, time of conversion. The final floating point representation is the sign, the real number or the mantissa, and the fraction, or exponent. This result, along with the floating point conversion from 22, are placed adjacent one another in word 24. One problem with this technique is that, since it is iterative, the time for conversion will vary, becoming longer as the size of the ASCII real number string increases.

The present invention relates to the conversion of numerical data in a vector processor. The unused leading characters are masked as zeros. Included in the algorithmic method is detection of the sign byte and assignment of a unique binary value to said sign byte depending on the sign being positive or negative. SIMD, vector processing architectures. These methods include identifying the beginning, ending, sign, and decimal point position of the real number in the ASCII string, extracting the decimal point, followed by taking each of the seven bit components of the ASCII real number, one character at a time, and subtracting the binary number, forty eight, to get the decimal numbers that make up the real number. ASCII string real number, said real number comprising a sign byte, an integer part, a fractional part, a decimal point separating the integer part from the fractional part, and a string terminator, to a binary decimal floating point real number representation on a vector processor. Also included is the parallel detection of the string terminator and masking of all unused characters as well as parallel detection of the decimal point that separates the integer part of the number from the fractional part of the number. Then the decimal point is stripped, while the integer is shifted one position to the right and a leading zero is inserted in the leftmost position as shown in 8 to form an eleven digit real number with no decimal point. Subsequent steps include, parallel conversion of all characters of the string into corresponding binary decimal values, parallel multiplication of each of the binary decimal values with a power of ten corresponding to the placement of each of the binary decimal values inside the decimal number to obtain individual binary results, an aggregation of the individual binary results of the parallel multiplication into a first intermediate binary result, multiplication of the first intermediate binary result with a floating point power of ten corresponding to a placement of the decimal point to obtain a second intermediate binary result, and multiplication of the second intermediate binary result with the binary value assigned to the sign to get a final floating point binary decimal result.

It is a further object of this invention to provide a vector processor architecture, selection of code, and a method for converting a signed ASCII real number of any size to a signed, floating point, binary decimal real number in a vector processor wherein the conversion time will be constant regardless of the size of the ASCII real number within a given range of sizes provided for by the vector processor architecture. The ASCII real number value can be any value equal to, less than or greater than zero and comprising any number of digits, with an integer, a fractional part, and a decimal point between the integer and the fractional part. In the example of FIG. The floating point conversion results, from numbers in 19 and 20, are placed adjacent each other in word, 23. The code comprises a fixed sequence of a constant number of instructions. While the invention does not impose, upon the method, code, or architecture, the use of single instruction, it is yet a further objective of the invention to provide a vector processor capable of the conversion using a single instruction. Another problem is that code for performing the conversion function involves branching and the use of multiple instructions, also adding to the execution time and efficiency of the conversion, due to latency issues. In step 12, the left, half word in 23 is vector multiplied by ten to the power of twelve, represented in floating point as 1000000000000.

ASCII format to a decimal real number in floating point binary decimal format in a vector processor are described. Commodity microprocessors tackle this problem by iterating over the individual digits of the real number and accumulate the partial result until a decimal point delimiter character or a string delimiter character is found, which ends the process. Methods for conversion of a real number from ASCII to binary floating point within a processor are known. The basic hypothesis of this volume is that currency patterns may tell us something about the spread of wage payments in specific societies in history. As far as wages are paid in currency, in particular in coin, specific patterns of denominations produced and used in space and time may provide insights. Data, image, audio, and video processing, some or all of which are present in all electronic devices today, are complex programming environments. Multimedia processing demands efficient programming in order to optimize functionality.